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lt3011 1 3011f output current (ma) 0 250 300 350 40 3011 ta02 200150 10 20 30 50 100 50 0 dropout voltage (mv) n wide input voltage range: 3v to 80v n low quiescent current: 46a n low dropout voltage: 300mv n output current: 50ma n pwrgd flag with programmable delay n no protection diodes needed n adjustable output from 1.24v to 60v n 1a quiescent current in shutdown n stable with 1f output capacitor n stable with ceramic, tantalum, and aluminum capacitors n reverse-battery protection n no reverse current flow from output to input n thermal limiting n thermally enhanced 12-lead msop and 10-pin (3mm 3mm) dfn packages typical application features applications description 50ma, 3v to 80v low dropout micropower linear regulator with pwrgd the lt ? 3011 is a high voltage, micropower, low dropout linear regulator. the device is capable of supplying 50ma of output current with a dropout voltage of 300mv. designed for use in battery-powered high voltage systems, the low quiescent current (46a operating and 1a in shutdown) is well controlled in dropout, making the lt3011 an ideal choice. the lt3011 includes a pwrgd ? ag to indicate output regulation. the delay between regulated output level and ? ag indication is programmable with a single capacitor. the lt3011 also has the ability to operate with very small output capacitors; it is stable with only 1f on the output. small ceramic capacitors can be used without the addition of any series resistance (esr) as is common with other regulators. internal protection circuitry includes reverse- battery protection, current limiting, thermal limiting, and reverse current protection. the lt3011 features an adjustable output with a 1.24v reference voltage. the device is available in the thermally enhanced 12-lead msop and the low pro? le (0.75mm) 10-pin (3mm 3mm) dfn package, both providing excel- lent thermal characteristics. 5v supply with shutdown n low current high voltage regulators n regulator for battery-powered systems n telecom applications n automotive applications dropout voltage , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 1 f v in 3v to80v 3011 ta01 v out 5v50ma v shdn <0.3v>2.0v output off on 1f 750k249k 1.6m in lt3011 shdn pwrgd out adj c t gnd 1000pf power good downloaded from: http:///
lt3011 2 3011f absolute maximum ratings in pin voltage .........................................................80v out pin voltage ......................................................60v input-to-output differential voltage ........................80v adj pin voltage ........................................................7v shdn pin voltage ...................................................80v c t pin voltage .................................................. 7v, C0.5v pwrgd pin voltage ....................................... 80v, C0.5v output short-circuit duration .......................... inde? nite (note 1) top view dd package 10-lead (3mm s 3mm) plastic dfn 10 11 96 7 8 45 3 2 1 innc shdn nc c t out adj gnd nc pwrgd t jmax = 150c, ja = 43c/w, jc = 16c/w exposed pad (pin 11) is gnd, must be soldered to pcb 12 3 4 5 6 nc out adj gnd nc pwrgd 1211 10 9 8 7 13 ncin nc shdn nc c t top view mse package 12-lead plastic msop t jmax = 150c, ja = 40c/w, jc = 16c/w exposed pad (pin 13) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range lt3011edd#pbf lt3011edd#trpbf ldkq 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3011idd#pbf lt3011idd#trpbf ldkq 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3011emse#pbf lt3011emse#trpbf 3011 12-lead plastic msop C40c to 125c lt3011hmse#pbf lt3011hmse#trpbf 3011 12-lead plastic msop C40c to 150c lt3011imse#pbf lt3011imse#trpbf 3011 12-lead plastic msop C40c to 125c lead based finish tape and reel part marking* package description temperature range lt3011edd lt3011edd#tr ldkq 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3011idd lt3011idd#tr ldkq 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3011emse lt3011emse#tr 3011 12-lead plastic msop C40c to 125c lt3011hmse lt3011hmse#tr 3011 12-lead plastic msop C40c to 150c lt3011imse lt3011imse#tr 3011 12-lead plastic msop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ storage temperature range ................... C65c to 150c operating junction temperature (notes 3, 10, 11) lt3011e, lt3011i .............................. C40c to 125c lt3011h ............................................ C40c to 150c lead temperature (soldering, 10 sec) mse package only ............................................ 300c downloaded from: http:///
lt3011 3 3011f parameter conditions min typ max units minimum input voltage i load = 50ma l 2.8 4 v adj pin voltage (notes 2, 3) v in = 3v, i load = 1ma 4v < v in < 80v, 1ma < i load < 50ma l 1.2281.215 1.241.24 1.2521.265 vv line regulation (note 2) v in = 3v to 80v, i load = 1ma l 11 2 m v load regulation (note 2) v in = 4v, i load = 1ma to 50ma v in = 4v, i load = 1ma to 50ma l 61 5 25 mvmv dropout voltage v in = v out(nominal) (notes 4, 5) i load = 1ma i load = 1ma l 100 150 190 mvmv i load = 10ma i load = 10ma l 200 260 350 mvmv i load = 50ma i load = 50ma l 300 370 550 mvmv gnd pin currentv in = v out(nominal) (notes 4, 6) i load = 0ma i load = 1ma i load = 10ma i load = 50ma ll l l 46 105410 1.9 90 200700 3.3 aa a ma output voltage noise c out = 10f, i load = 50ma, bw = 10hz to 100khz, v out = 1.24v 100 v rms adj pin bias current (note 7 ) 30 100 na shutdown threshold v out = off to on v out = on to off ll 0.3 1.31.1 2v v shdn pin current (note 8) v shdn = 0v v shdn = 6v 0.50.1 2 0.5 aa quiescent current in shutdown v in = 6v, v shdn = 0v 1 5 a pwrgd trip point % of nominal output voltage, output rising l 85 90 94 % pwrgd trip point hysteresis % of nominal output voltage 1.1 % pwrgd output low voltage i pwrgd = 50a l 140 250 mv c t pin charging current l 36 a c t pin voltage differential v ct(pwrgd high) C v ct(pwrgd low) 1.67 v ripple rejection v in = 7v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load = 50ma 65 85 db current limit v in = 7v, v out = 0v v in = 4v, v out = C0.1v (note 2) l 60 140 ma ma input reverse leakage current v in = C80v, v out = 0v l 6m a reverse output current (note 9) v out = 1.24v, v in < 1.24v (note 2) 8 15 a electrical characteristics the l denotes the speci? cations which apply over the C40c to 125c operating temperature range, otherwise speci? cations are t j = 25c. (lt3011e, lt3011i) parameter conditions min typ max units minimum input voltage i load = 50ma l 2.8 4 v adj pin voltage (notes 2, 3) v in = 3v, i load = 1ma 4v < v in < 80v, 1ma < i load < 50ma l 1.2281.215 1.241.24 1.2521.265 vv line regulation (note 2) v in = 3v to 80v, i load = 1ma l 11 2 m v load regulation (note 2) v in = 4v, i load = 1ma to 50ma v in = 4v, i load = 1ma to 50ma l 61 5 25 mvmv electrical characteristics the l denotes the speci? cations which apply over the C40c to 150c operating temperature range, otherwise speci? cations are t j = 25c. (lt3011h) downloaded from: http:///
lt3011 4 3011f parameter conditions min typ max units dropout voltage v in = v out(nominal) (notes 4, 5) i load = 1ma i load = 1ma l 100 150 220 mvmv i load = 10ma i load = 10ma l 200 260 380 mvmv i load = 50ma i load = 50ma l 300 370 575 mvmv gnd pin currentv in = v out(nominal) (notes 4, 6) i load = 0ma i load = 1ma i load = 10ma i load = 50ma ll l l 46 105410 1.9 125225 750 3.5 aa a ma output voltage noise c out = 10f, i load = 50ma, bw = 10hz to 100khz, v out = 1.24v 100 v rms adj pin bias current (note 7) 30 100 na shutdown threshold v out = off to on v out = on to off ll 0.3 1.31.1 2v v shdn pin current (note 8) v shdn = 0v v shdn = 6v 0.50.1 2 0.5 aa quiescent current in shutdown v in = 6v, v shdn = 0v 1 5 a pwrgd trip point % of nominal output voltage, output rising l 85 90 95 % pwrgd trip point hysteresis % of nominal output voltage 1.1 % pwrgd output low voltage i pwrgd = 50a l 140 250 mv c t pin charging current l 36 a c t pin voltage differential v ct(pwrgd high) C v ct(pwrgd low) 1.67 v ripple rejection v in = 7v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load = 50ma 65 85 db current limit v in = 7v, v out = 0v v in = 4v, v out = C0.1v (note 2) l 60 140 ma ma input reverse leakage current v in = C80v, v out = 0v l 6m a reverse output current (note 9) v out = 1.24v, v in < 1.24v (note 2) 8 15 a electrical characteristics (lt3011h) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3011 is tested and speci? ed for these conditions with the adj pin connected to the out pin.note 3: operating conditions are limited by maximum junction temperature. the regulated output voltage speci? cation will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited. note 4: to satisfy requirements for minimum input voltage, the lt3011 is tested and speci? ed for these conditions with an external resistor divider (249k bottom, 409k top) for an output voltage of 3.3v. the external resistor divider will add a 5a dc load on the output. note 5: dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a speci? ed output current. in dropout, the output voltage will be equal to (v in C v dropout ). note 6: gnd pin current is tested with v in = v out(nominal) and a current source load. this means the device is tested while operating close to its dropout region. this is the worst-case gnd pin current. the gnd pin current will decrease slightly at higher input voltages. note 7: adj pin bias current ? ows into the adj pin. note 8: shdn pin current ? ows out of the shdn pin. note 9: reverse output current is tested with the in pin grounded and the out pin forced to the rated output voltage. this current ? ows into the out pin and out the gnd pin. note 10: the lt3011 regulators are tested and speci? ed under pulse load conditions such that t j ? t a . the lt3011e regulators are 100% tested at t a = 25c. performance of the lt3011e over the full C40c to 125c operating junction temperature range is assured by design, characterization and correlation with statistical process controls. the lt3011i regulators are guaranteed over the full C40c to 125c operating junction temperature range. the lt3011h is tested to the lt3011h electrical characteristics table at 150c operating junction temperature. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 11: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c (lt3011e/lt3011i) or 150c (lt3011h) when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. the l denotes the speci? cations which apply over the C40c to 150c operating temperature range, otherwise speci? cations are at t j = 25c. downloaded from: http:///
lt3011 5 3011f typical performance characteristics dropout voltage guaranteed dropout voltage dropout voltage quiescent current adj pin voltage quiescent current gnd pin current gnd pin current vs i out shdn pin threshold output current (ma) 0 dropout voltage (mv) 200 400 600100 300 500 10 20 30 40 3011 g02 50 5 01 52 53 54 5 = test points t j b 125 o c t j b 25 o c t j = 25c, unless otherwise noted. input voltage (v) 0 gnd pin current (ma) 1.2 1.6 2.0 8 3011 g07 0.80.4 1.0 1.4 1.80.6 0.2 0 2 14 36 79 51 0 t j = 25c *for v out = 1.24v r l = 24.8 i l = 50ma* r l = 49.6 i l = 25ma* r l = 124 i l = 10ma* r l = 1.24k, i l = 1ma* input voltage (v) 0 quiescent current (a) 50 60 70 7 4030 24 19 35 8 61 0 10 0 20 80 3011 g06 v shdn = v in t j = 25c r l = d output current (ma) 0 dropout voltage (mv) 250 300 350 200150 10 20 40 30 50 50 0 100 400 3011 g01 t j 125 o c t j 25 o c temperature (c) C50 0 dropout voltage (mv) 100 200 C25 0 25 50 100 75 125 300 400 50 150 250 350 150 3011 g03 i l = 50ma i l = 10ma i l = 1ma temperature (c) C50 1.230 adj pin voltage (v) 1.234 1.238 1.242 C25 0 25 50 100 75 125 1.246 1.250 1.232 1.236 1.240 1.244 1.248 150 3011 g05 i l = 1ma temperature (c) C50 quiescent current (a) 70 25 3011 g04 4020 C25 0 50 10 0 8060 50 30 75 100 125 150 v shdn = v in v shdn = gnd v in = 6v r l = i l = 0 output current (ma) 0 gnd pin current (ma) 1.2 1.6 2.0 40 3011 g08 0.80.4 1.0 1.4 1.80.6 0.2 0 10 52 0 15 30 35 45 25 50 v in = v out(nominal) +1v t j = 25c temperature (c) C50 shdn pin threshold (v) 1.4 25 3011 g09 0.80.4 C25 0 50 0.2 0 1.61.2 1.0 0.6 75 100 125 150 downloaded from: http:///
lt3011 6 3011f typical performance characteristics shdn pin current shdn pin current adj pin bias current pwrgd trip point pwrgd output low voltage c t charging current c t comparator threshold current limit current limit t j = 25c, unless otherwise noted. shdn pin voltage (v) 0 shdn pin current (a) 0.16 0.20 0.24 3.5 0.120.08 12 0.5 4.5 1.5 2.5 4 35 0.04 0 0.28 3011 g10 t j = 25c current flows out of shdn pin temperature (c) shdn pin current (a) 3011 g11 0.40.2 0.1 0 0.60.5 0.3 C50 0 50 75 C25 25 100 150 125 v shdn = 0v current flows out of shdn pin temperature (c) adj pin bias current (na) 3011 g12 8040 20 0 120100 60 C50 0 50 75 C25 25 100 150 125 temperature (c) C50 85 pwrgd trip point (% of output voltage) 87 89 91 C25 0 25 50 100 75 125 93 95 86 88 90 92 94 150 3011 g13 output rising output falling temperature (c) C50 0 current limit (ma) 40 80 120 C25 0 25 50 100 75 125 160 200 20 60 100 140 180 150 3011 g18 v in = 7v v out = 0v input voltage (v) 0 current limit (ma) 40 80 120 160 20 60 100 140 180 3011 g17 07 24 19 35 8 61 0 v out = 0v t j = 25c temperature (c) C50 0 c t comparator threshold (v) 0.4 0.8 1.2 C25 0 25 50 100 75 125 1.6 2.0 0.2 0.6 1.0 1.4 1.8 150 3011 g16 v ct(high) v ct(low) temperature (c) C50 c t charging current (a) 3.5 25 3011 g15 2.01.0 C25 0 50 0.5 0 4.03.0 2.5 1.5 75 100 125 150 pwrgd tripped high temperature (c) C50 0 pwrgd output low voltage (mv) 40 80 120 C25 0 25 50 100 75 125 160 200 20 60 100 140 180 150 3011 g14 i pwrgd = 50a downloaded from: http:///
lt3011 7 3011f typical performance characteristics reverse output current reverse output current input ripple rejection input ripple rejection minimum input voltage load regulation output noise spectral density output noise (10hz to 100khz) transient response frequency (hz) 10 0.001 output noise spectral density (v/ hz) 0.1 10 1k 10k 100 100k 3011 g25 0.01 1 v out = 1.24v c out = 1f i l = 50ma t j = 25c, unless otherwise noted. 3011 g26 1ms/div v out 100v/div v out = 1.24v c out = 1f i l = 50ma worst-case noise time (s) 0 700 200 400 100 900 300 500 800 600 1000 3011 g27 v in = 6v v out set for 5v c in = 1f ceramic c out = 1f ceramic i load = 1ma to 50ma output voltage deviation (v) load current (ma) 0 0.1 0.2 C0.1C0.2 25 0 50 0.3 output voltage (v) 07 24 19 35 8 61 0 3011 g19 t j = 25c v in = 0v current flows into output pin v out = v adj reverse output current (a) 100 120 140 8060 20 0 40 160 adj pin clamp (see applications information) frequency (hz) 30 ripple rejection (db) 50 80 10 100 100k 1m 0 10 1k 10k 100 70 9040 6020 3011 g22 v in = 7v + 50mv rms ripple i l = 50ma, v out = 1.24v c out = 10f ceramic c out = 1f ceramic temperature (c) C50 reverse output current (a) 70 25 3011 g20 4020 C25 0 50 10 0 8060 50 30 75 100 125 150 v in = 0v v out = v adj = 1.24v temperature (c) C50 70 ripple rejection (db) 74 78 82 C25 0 25 50 100 75 125 86 90 72 76 80 84 88 150 3011 g21 v in = 7v + 0.5v p-p ripple at f = 120hz i l = 50ma v out = 1.24v temperature (c) C50 minimum input voltage (v) 3.5 25 3011 g23 2.01.0 C25 0 50 0.5 0 4.03.0 2.5 1.5 75 100 125 150 i l = 50ma temperature (c) load regulation (mv) 3011 g24 C4C8 C10C12 0 C2C6 C50 0 50 75 C25 25 100 150 125 i l = 1ma to 50ma v out = 1.24v downloaded from: http:///
lt3011 8 3011f pin functions out (pin 1/pin 2): output. the output supplies power to the load. a minimum output capacitor of 1f is required to prevent oscillations. larger capacitors will be required for applications with large transient loads to limit peak voltage transients. see the applications information section for more information on output capacitance and reverse output characteristics. adj (pin 2/pin 3): adjust. this is the input to the error ampli? er. this pin is internally clamped to 7v. it has a bias current of 30na which ? ows into the pin (see the curve labeled adj pin bias current vs temperature in the typical performance characteristics section). the adj pin voltage is 1.24v referenced to ground, and the output voltage range is 1.24v to 60v. gnd (pins 3, 11/pins 4, 13): ground. the exposed back- side of the package (pin 11/pin 13) is an electrical connec-tion for gnd. as such, to ensure optimum device opera- tion and thermal performance, the exposed pad must be connected directly to pin 3/pin 4 on the pc board. nc (pins 4, 7, 9/pins 1, 5, 8, 10, 12): no connection. these pins have no internal connection. connecting nc pins to a copper area for heat dissipation provides a small improvement in thermal performance. pwrgd (pin 5/pin 6): power good. the pwrgd ? ag is an open-collector ? ag to indicate that the output voltage has increased above 90% of the nominal output voltage. there is no internal pull-up on this pin; a pull-up resistor must be used. the pwrgd pin will change state from an open-collector pull-down to high impedance after both the output is above 90% of the nominal voltage and the capacitor on the c t pin has charged through a 1.67v dif- ferential. the maximum pull-down current of the pwrgd pin in the low state is 50a. c t (pin 6/pin 7): timing capacitor. the c t pin allows the use of a small capacitor to delay the timing between the point where the output crosses the pwrgd threshold and the pwrgd ? ag changes to a high impedance state. cur- rent out of this pin during the charging phase is 3a. the voltage difference between the pwrgd low and pwrgd high states is 1.67v (see the applications information section). shdn (pin 8/pin 9): shutdown. the shdn pin is used to put the lt3011 into a low power shutdown state. the output will be off when the shdn pin is pulled low. the shdn pin can be driven either by 5v logic or open-collector logic with a pull-up resistor. the pull-up resistor is only required to supply the pull-up current of the open-collec- tor gate, normally several microamperes. if unused, the shdn pin must be tied to a logic high or v in . in (pin 10/pin 11): input. power is supplied to the device through the in pin. a bypass capacitor is required on this pin if the device is more than six inches away from the main input ? lter capacitor. in general, the output imped- ance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. a bypass capacitor in the range of 1f to 10f is suf? cient. the lt3011 is designed to withstand reverse voltages on the in pin with respect to ground and the out pin. in the case of a reverse input voltage, which can occur if a battery is plugged in backwards, the lt3011 will act as if there is a diode in series with its input. there will be no reverse current ? ow into the lt3011 and no reverse volt- age will appear at the load. the device will protect both itself and the load. exposed pad (pin 11/pin 13): ground. the exposed pad must be soldered to the pcb. (dfn/msop) downloaded from: http:///
lt3011 9 3011f applications information the lt3011 is a 50ma high voltage/low dropout regulator with micropower quiescent current and shutdown. the device is capable of supplying 50ma at a dropout voltage of 300mv. the low operating quiescent current (46a) drops to 1a in shutdown. in addition to low quiescent current, the lt3011 incorporates several protection features which make it ideal for use in battery-powered systems. the device is protected against both reverse input and reverse output voltages. in battery backup applications where the output can be held up by a backup battery when the input is pulled to ground, the lt3011 acts like it has a diode in series with its output and prevents reverse current ? ow. adjustable operation the lt3011 has an output voltage range of 1.24v to 60v. the output voltage is set by the ratio of two external resistors as shown in figure 1. the device servos the output to maintain the voltage at the adjust pin at 1.24v referenced to ground. the current in r1 is then equal to 1.24v/r1 and the current in r2 is the current in r1 plus the adj pin bias current. the adj pin bias current, 30na at 25c, ? ows through r2 into the adj pin. the output voltage can be calculated using the formula in figure 1. the value of r1 should be less than 250k to minimize errors in the output voltage caused by the adj pin bias current. note that in shutdown the output is turned off and the divider current will be zero. the adjustable device is tested and speci? ed with the adj pin tied to the out pin and a 5a dc load (unless otherwise speci? ed) for an output voltage of 1.24v. speci- ? cations for output voltages greater than 1.24v will be proportional to the ratio of the desired output voltage to 1.24v; (v out /1.24v). for example, load regulation for an output current change of 1ma to 50ma is C6mv (typical) at v out = 1.24v. at v out = 12v, load regulation is: 12 124 65 8 v v mv mv . ?? ? = output capacitance and transient response the lt3011 is designed to be stable with a wide range of output capacitors. the esr of the output capacitor affects stability, most notably with small capacitors. a minimum output capacitor of 1f with an esr of 3 or less is recommended to prevent oscillations. the lt3011 is a micropower device and output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the lt3011, will increase the effective output capacitor value. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are speci? ed with eia temperature char- acteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances v in 3011 f01 v out r2r1 + r2r1 v out = v adj v adj = 1.24v i adj = 30na at 25 o c output range = 1.24v to 60v + (i adj )(r2) 1 + in lt3011 out adj gnd figure 1. adjustable operation downloaded from: http:///
lt3011 10 3011f applications information in a small package, but they tend to have strong voltage and temperature coef? cients, as shown in figures 2 and 3. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied and over the operating tempera- ture range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is avail- able in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signi? cant enough to drop capacitor values below appropriate levels. capaci-tor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be veri? ed. voltage and temperature coef? cients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, simi- lar to the way piezoelectric accelerometer or microphone works. for a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. pwrgd flag and timing capacitor delay the pwrgd ? ag is used to indicate that the adj pin volt- age is within 10% of the regulated voltage. the pwrgd pin is an open-collector output, capable of sinking 50a of current when the adj pin voltage is low. there is no internal pull-up on the pwrgd pin; an external pull-up resistor must be used. when the adj pin rises to within 10% of its ? nal reference value, a delay timer is started. at the end of this delay, programmed by the value of the capacitor on the c t pin, the pwrgd pin switches to a high impedance and is pulled up to a logic level by an external pull-up resistor. to calculate the capacitor value on the c t pin, use the following formula: c it vv time ct delay ct high ct low = ? ? () () figure 4 shows a block diagram of the pwrgd circuit. at start-up, the timing capacitor is discharged and the pwrgd pin will be held low. as the output voltage increases and the adj pin crosses the 90% threshold, the jk ? ip? op is reset, and the 3a current source begins to charge the timing capacitor. once the voltage on the c t pin reaches the v ct(high) threshold (approximately 1.7v at 25c), the capacitor voltage is clamped and the pwrgd pin is set to a high impedance state. dc bias voltage (v) change in value (%) 3011 f02 20 0 C20C40 C60 C80 C100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v,1210 case size, 10 m f temperature ( o c) C50 4020 0 C20C40 C60 C80 C100 25 75 3011 f03 C25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v,1210 case size, 10 m f figure 2. ceramic capacitor dc bias characteristics figure 3. ceramic capacitor temperature characteristics downloaded from: http:///
lt3011 11 3011f during normal operation, an internal glitch ? lter will ignore short transients (<15s). longer transients below the 90% threshold will reset the jk ? ip-? op. this ? ip-? op ensures that the capacitor on the c t pin is quickly discharged all the way to the v ct(low) threshold before restarting the time delay. this provides a consistent time delay after the adj pin is within 10% of the regulated voltage before the pwrgd pin switches to high impedance. thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125c, lt3011e/ lt3011i or 150c, lt3011h). the power dissipated by the device will be made up of two components: 1. output current multiplied by the input/output voltage differential: i out ? (v in C v out ) and, 2. gnd pin current multiplied by the input voltage: i gnd ? v in the gnd pin current is found by examining the gnd pin current curves in the typical performance characteristics section. power dissipation will be equal to the sum of the two components listed above. the lt3011 series regulators have internal thermal limiting designed to protect the device during overload conditions. for continuous normal conditions, the maximum junction temperature rating of 125c (lt3011e/ lt3011i) or 150c (lt3011h) must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. qj k v ref ? 90% adj v ct(low) z 0.1v v ct(high) C v be ( z 1.1v) i ct 3a c t 3011 f04 C + C + pwrgd for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener- ated by power devices. the following table lists thermal resistance for several different board sizes and copper areas. all measurements were taken in still air on 3/32" fr-4 board with one ounce copper. table 1. msop measured thermal resistance copper area board area thermal resistance (junction-to-ambient) topside backside 2500 sq mm 2500 sq mm 2500 sq mm 52c/w 1000 sq mm 2500 sq mm 2500 sq mm 54c/w 225 sq mm 2500 sq mm 2500 sq mm 58c/w 100 sq mm 2500 sq mm 2500 sq mm 64c/w table 2. dfn measured thermal resistance copper area board area thermal resistance (junction-to-ambient) topside backside 2500 sq mm 2500 sq mm 2500 sq mm 52c/w 1000 sq mm 2500 sq mm 2500 sq mm 54c/w 225 sq mm 2500 sq mm 2500 sq mm 58c/w 100 sq mm 2500 sq mm 2500 sq mm 64c/w the thermal resistance junction-to-case ( jc ), measured at the exposed pad on the back of the die, is 16c/w. continuous operation at large input/output voltage dif- ferentials and maximum load current is not practical due to thermal limitations. transient operation at high input/ output differentials is possible. the approximate thermal time-constant for a 2500sq mm 3/32" fr-4 board, with maximum topside and backside area for one ounce cop- per, is three seconds. this time-constant will increase as more thermal mass is added (i.e., vias, larger board and other components). for an application with transient high power peaks, average power dissipation can be used for junction temperature calculations as long as the pulse period is signi? cantly less than the thermal time constant of the device and board. figure 4. pwrgd circuit block diagram applications information downloaded from: http:///
lt3011 12 3011f calculating junction temperature example 1: given an output voltage of 5v, an input volt- age range of 24v to 30v, an output current range of 0ma to 50ma, and a maximum ambient temperature of 50c, what will the maximum junction temperature be? the power dissipated by the device will be equal to: i out(max) ? (v in(max) C v out ) + (i gnd ? v in(max) ) where: i out(max) = 50ma v in(max) = 30v i gnd at (i out = 50ma, v in = 30v) = 1ma so: p = 50ma ? (30v C 5v) + (1ma ? 30v) = 1.28w the thermal resistance will be in the range of 52c/w to 64c/w depending on the copper area. so, the junction temperature rise above ambient will be approximately equal to: 1.28w ? 58c/w = 74c the maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: t jmax = 50c + 74c = 124c example 2: given an output voltage of 5v, an input voltage of 48v that rises to 72v for 5ms (max) out of every 100ms, and a 5ma load that steps to 50ma for 50ms out of every 250ms, what is the junction temperature rise above ambi- ent? using a 500ms period (well under the time-constant of the board), power dissipation is as follow: p1 (48v in , 5ma load) = 5ma ? (48v C 5v) + (200a ? 48v) = 0.23w p2 (48v in , 50ma load) = 50ma ? (48v C 5v) + (1ma ? 48v) = 2.20w p3 (72v in , 5ma load) = 5ma (72v C 5v) + (200a ? 72v) = 0.35w p1 (72v in , 50ma load) = 50ma (72v C 5v) + (1ma ? 72v) = 3.42w operation at the different power levels is as follows: 76% operation at p1, 19% for p2, 4% for p3, and 1% for p4. p eff = 76%(0.23w) + 19%(2.20w) + 4%(0.35w) + 1%(3.42w) = 0.64w with a thermal resistance in the range of 52c/w to 64c/w, this translates to a junction temperature rise above ambi- ent of 33c to 41c. high temperature operation care must be taken when designing lt3011 applications to operate at high ambient temperatures. the lt3011 works at elevated temperatures but erratic operation can occur due to unforeseen variations in external components. some tantalum capacitors are available for high temperature operation, but esr is often several ohms; capacitor esr above 3 is unsuitable for use with the lt3011. ceramic capacitor manufacturers (murata, avx, tdk and vishay vitramon at this writing) now offer ceramic capacitors that are rated to 150c using an x8r dielectric. device instability will occur if the output capacitor value and esr are outside design limits at elevated temperature and operating dc voltage bias (see information on capacitor characteristics under output capacitance and transient response). check each passive component for absolute value and voltage ratings over the operating temperature range. leakage in capacitors, or from solder ? ux left after insuf- ? cient board cleaning, adversely affects the low quies- cent current operation. consider junction temperature increase due to power dissipation in both the junction and nearby components to ensure maximum speci? ca- tions are not violated for the lt3011e/lt3011h/lt3011i or external components. protection features the lt3011 incorporates several protection features which make it ideal for use in battery-powered circuits. in ad- dition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse-input voltages, and reverse voltages from output-to-input. applications information downloaded from: http:///
lt3011 13 3011f current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. for normal opera- tion, the junction temperature should not exceed 125c (lt3011e/lt3011i) or 150c (lt3011h). the input of the device will withstand reverse voltages of 80v. current ? ow into the device will be limited to less than 6ma (typically less than 100a) and no negative voltage will appear at the output. the device will protect both itself and the load. this provides protection against batteries which can be plugged in backwards. the adj pin of the adjustable device can be pulled above or below ground by as much as 7v without damaging the device. if the input is left open-circuit or grounded, the adj pin will act like an open-circuit when pulled below ground, and like a large resistor (typically 100k) in series with a diode when pulled above ground. if the input is powered by a voltage source, pulling the adj pin below the reference voltage will cause the device to try and force the current limit out of the output. this will cause the output to go to an unregulated high voltage. pulling the adj pin above the reference voltage will turn off all output current. in situations where the adj pin is connected to a resistor divider that would pull the adj pin above its 7v clamp volt- age if the output is pulled high, the adj pin input current must be limited to less than 5ma. for example, a resistor divider is used to provide a regulated 1.5v output from the 1.24v reference when the output is forced to 60v. the top resistor of the resistor divider must be chosen to limit the current into the adj pin to less than 5ma when the adj pin is at 7v. the 53v difference between the out and adj pin is divided by the 5ma maximum current into the adj pin yields a minimum top resistor value of 10.6k. in circuits where a backup battery is required, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage, or is left open-circuit. current ? ow back into the output will follow the curve shown in figure 5. the rise in reverse output current above 7v occurs from the breakdown of the 7v clamp on the adj pin. with a resistor divider on the regula- tor output, this current will be reduced depending on the size of the resistor divider. when the in pin of the lt3011 is forced below the out pin or the out pin is pulled above the in pin, input cur- rent will typically drop to less than 2a. this can happen if the input of the lt3011 is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. the state of the shdn pin will have no effect on the reverse output current when the output is pulled above the input. output voltage (v) 07 24 19 35 8 61 0 3011 f05 t j = 25c v in = 0v current flows into output pin v out = v adj reverse output current (a) 100 120 140 8060 20 0 40 160 adj pin clamp (see above) figure 5. reverse output current applications information downloaded from: http:///
lt3011 14 3011f typical applications load current (a) 0 efficiency (%) 80 90 100 1.00 3011 ta04 70 60 50 0.25 0.50 0.75 1.25 v in = 10v v in = 42v v out = 5v l = 68 m h boost v in 6 210 12 d110mq060n r115.4k v out 5v1a/250ma 4 3, 11 10 85 12 1514 11 c c 1nf for input voltages below 7.5v, some restrictions may apply increase l1 to 30 m h for load currents above 0.6a and to 60 m h above 1a. lt3011 pin numbers are for the dd package. 1, 8, 9, 16 lt1766 shdnsync sw bias fb v c gnd c20.33 m f c1 100 m f 10v solid tantalum l1 ? 15 m h d2 d1n914 r24.99k 3011 ta03 750k 249k c34.7 m f 100vceramic v in 5.5v* to 60v + adj out in shdn pwrgd lt3011 gnd 6 c t operating current high low * ? 100k 1000pf + adj out in shdn lt3011 gnd on off 1 m f 1 m f 750k v in 12v (future 42v) load: clock, security system etc + C adj out in shdn lt3011 gnd on off 1 m f 1 m f v in 48v (72v transient) load: system monitor etc no protection diode needed! no protection diode needed! 3011 ta05 backup battery 249k 750k 249k 5v buck converter with low current keep alive backup buck converter ef? ciency vs load current lt3011 automotive application lt3011 telecom application downloaded from: http:///
lt3011 15 3011f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 3.00 0.10 (4 sides) note:1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50bsc 0.675 0.05 3.50 0.05 packageoutline 0.25 0.05 0.50 bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev b) dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) msop (mse12) 0608 rev b 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C?0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail b 1 6 note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 123456 3.00 p 0.102 (.118 p .004) (note 4) 0.406 p 0.076 (.016 p .003) ref 4.90 p 0.152 (.193 p .006) detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc downloaded from: http:///
lt3011 16 3011f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0808 printed in usa typical application in lt 3 0 1 1 shdn 1 m f return C48v out adj gnd 3011 ta06 1 m f r set i led = 1.24v/r set C48v can vary from C4v to C80v on off constant brightness for indicator led over wide input voltage range part number description comments lt1121/ lt1121hv 150ma, micropower, ldo v in : 4.2v to 30v/36v, v out(min) = 3.75v, v do = 0.42v, i q = 30a, i sd = 16a, reverse battery protection, sot-223, s8 and z packages lt1676 60v, 440ma (i out ), 100khz, high ef? ciency step-down dc/dc converter v in : 7.4v to 60v, v out(min) = 1.24v, i q = 3.2ma, i sd = 2.5a, s8 package lt1761 100ma, low noise micropower, ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.3v, i q = 20a, i sd <1a, low noise < 20v rms , stable with 1f ceramic capacitors, thinsot tm package lt1762 150ma, low noise micropower, ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.3v, i q = 25a, i sd <1a, low noise < 20v rms , ms8 package lt1763 500ma, low noise micropower, ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.3v, i q = 30a, i sd <1a, low noise < 20v rms , s8 package lt1764/ lt1764a 3a, low noise, fast transient response, ldo v in : 2.7v to 20v, v out(min) = 1.21v, v do = 0.34v, i q = 1ma, i sd <1a, low noise < 40v rms , a version stable with ceramic capacitors, dd and to220-5 packages lt1766 60v, 1.2a (i out ), 200khz, high ef? ciency step-down dc/dc converter v in : 5.5v to 60v, v out(min) = 1.2v, i q = 2.5ma, i sd = 25a, tssop-16/e package lt1776 40v, 550ma (i out ), 200khz, high ef? ciency step-down dc/dc converter v in : 7.4v to 40v, v out(min) = 1.24v, i q = 3.2ma, i sd = 30a, n8 and s8 packages lt1956 60v, 1.2a (i out ), 500khz, high ef? ciency step-down dc/dc converter v in : 5.5v to 60v, v out(min) = 1.2v, i q = 2.5ma, i sd = 25a, tssop-16/e package lt1962 300ma, low noise micropower, ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.27v, i q = 30a, i sd <1a, low noise < 20v rms , ms8 package lt1963/ lt1963a 1.5a, low noise, fast transient response, ldo v in : 2.1v to 20v, v out(min) = 1.21v, v do = 0.34v, i q = 1ma, i sd <1a, low noise < 40v rms , a version stable with ceramic capacitors, dd, to220-5, s0t-223 and s8 packages lt1965 1.1a, low noise, low dropout linear regulator 310mv dropout voltage, low noise = 40v rms , v in : 1.8v to 20v, v out : 1.2v to 19.5v, stable with ceramic capacitors, to-220, ddpak, msop and 3mm 3mm dfn packages lt3009 20ma, 3a i q micropower ldo 280mv dropout voltage, low i q = 3a, v in : 1.6v to 20v, thinsot and sc-70 packages lt3010/ lt3010h 50ma, 3v to 80v, low noise micropower ldo v in : 3v to 8v, v out(min) = 1.275v, v do = 0.3v, i q = 30a, i sd = 1a, low noise < 100v rms , ms8e package, h grade = +140c t jmax lt3012/ lt3012h 250ma, 4v to 80v, low dropout micropower linear regulator v in : 4v to 80v, v out : 1.24v to 60v, v do = 0.4v, i q = 40a, i sd <1a, tssop-16e and 4mm 3mm dfn-12 packages, h grade = +140c t jmax lt3013/ lt3013h 250ma, 4v to 80v, low dropout micropower linear regulator v in : 4v to 80v, v out : 1.24v to 60v, v do = 0.4v, i q = 65a, i sd <1a, tssop-16e and 4mm 3mm dfn-12 packages, h grade = +140c t jmax , pwrgd flag lt3014/hv 20ma, 3v to 80v, low dropout micropower linear regulator v in : 3v to 80v (100v for 2ms, hv version), v out : 1.22v to 60v, v do = 0.35v, i q = 7a, i sd <1a, thinsot and 3mm 3mm dfn-8 packages lt3080/ lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise = 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with one resistor v out set; directly parallelable (no op amp required), stable with ceramic capacitors, to-220, sot-223, msop and 3mm 3mm dfn packages; lt3080-1 features an integrated ballast resistor thinsot is a trademark of linear technology corporation. related parts downloaded from: http:///

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